Segmentation and Paging in the Intel IA-32 Processors

Note: I wrote this as a forum post for one of my graduate courses. I’m sharing it here just in case anyone else finds it interesting. –Ron

16-bit Processors and Segmentation (1978)

The IA-32 architecture family was preceded by 16-bit processors, the 8086 and 8088. The 8086 has 16-bit registers and a 16-bit external data bus, with 20-bit addressing giving a 1-MByte address space. The 8088 is similar to the 8086 except it has an 8-bit external data bus.

The 8086/8088 introduced segmentation to the IA-32 architecture. With segmentation, a 16-bit segment register contains a pointer to a memory segment of up to 64 KBytes. Using four segment registers at a time, 8086/8088 processors are able to address up to 256 KBytes without switching between segments. The 20-bit addresses that can be formed using a segment register and an additional 16-bit pointer provide a total address range of 1 MByte.

The Intel 286 Processor (1982)

The Intel 286 processor introduced protected mode operation into the IA-32 architecture. Protected mode uses the segment register content as selectors or pointers into descriptor tables. Descriptors provide 24-bit base addresses with a physical memory size of up to 16 MBytes, support for virtual memory management on a segment swapping basis, and a number of protection mechanisms.

The Intel 386 Processor (1985)

The Intel 386 processor has a 32-bit address bus that supports up to 4-GBytes of physical memory. It has a segmented-memory model and a flat memory model. The 386 introduced paging, with a fixed 4-KByte page size, providing a method for virtual memory management.

The Intel Pentium Processor (1993)

The pentium added extensions to make the virtual-8086 mode more efficient and allow for 4-MByte as well as 4-KByte pages. This feature is known as Page Size Extension (PSE). The PSE allows for page sizes of 4 MB to exist along with 4KB pages.

The motivation for the larger page size
Assume that a task will be accessing a large buffer in memory and that it is the OS’s intention that the processor should follow the same rules of conduct when accessing any location(s) in this buffer. As an example, assume it is a 2MB video frame buffer in memory. Using 386-compatible paging, the OS would have to set up 512 PTE’s, each one associated with a 4KB page within the buffer and each one with identical attribute bit settings (i.e., the attribute bits that define the processor rules of conduct within the page). Setting up and maintaining 512 PTEs is a lot of housekeeping.

Sources

Intel (2009). Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture

Shanley, Tom, & Colwell, Bob (2004). The Unabridged Pentium 4 IA32 Processor Genealogy. Addison-Wesley Professional